Stress-Induced Leakage Current in p+ Poly MOS Capacitors with Poly-Si and Poly-Si0.7Ge0.3 Gate Material

The gate bias polarity dependence of stress-induced leakage current (SILC) of PMOS capacitors with a p+ polycrystalline silicon (poly-Si) and polycrystalline Silicon-Germanium (poly-Si0.7 Ge0.3) gate on 5.6-nm thick gate oxides has been investigated. It is shown that the SILC characteristics are highly asymmetric with gate bias polarity. This asymmetric behavior is explained by the occurrence of a different injection mechanism for negative bias, compared to positive bias where Fowler-Nordheim (FN) tunneling is the main conduction mechanism. For gate injection, a larger oxide field is required to obtain the same tunneling current, which leads to reduced SILC at low fields. Moreover, at negative gate bias, the higher valence band position of poly-SiGe compared to poly-Si reduces the barrier height for tunneling to traps and hence leads to increased SILC. At positive gate bias, reduced SILC is observed for poly-SiGe gates compared to poly-Si gates. This is most likely due to a lower concentration of Boron in the dielectric in the case of poly-SiGe compared to poly-Si. This makes Boron-doped poly-SiGe a very interesting gate material for nonvolatile memory device

Diffusion and electrical properties of Boron and Arsenic doped poly-Si and poly-GexSi1−x(x 0.3)Ge_xSi_1-x(x~0.3) as gate material for sub-0.25 µm complementary metal oxide semiconductor applications

In this paper the texture, morphology, diffusion and electrical (de‐) activation of dopants in polycrystalline GexSi1-x and Si have been studied in detail. For gate doping B+,BF2+ and As+ were used and thermal budgets were chosen to be compatible with deep submicron CMOS processes. Diffusion of dopants is different for GeSi alloys, B diffuses significantly more slowly and As has a much faster diffusion in GeSi. For B doped samples both electrical activation and mobility are higher compared to poly‐Si. Also for the first time, BF2+ data of doped layers are presented, these show the same trend as the B doped samples but with an overall higher sheet resistance. For arsenic doping, activation and mobility are lower compared to poly‐Si, resulting in a higher sheet resistance. The dopant deactivation due to long low temperature steps after the final activation anneal is also found to be quite different. Boron‐doped GeSi samples show considerable reduced deactivation whereas arsenic shows a higher deactivation rate. The electrical properties are interpreted in terms of different grain size, quality and properties of the grain boundaries, defects, dopant clustering, and segregation, and the solid solubility of the dopants

Low hydrogen content silicon nitride films deposited at room temperature with a multipolar ECR plasma source

Silicon nitride layers with very low hydrogen content (less than 1 atomic percent) were deposited at near room temperature, from N2 and SiH4, with a multipolar electron cyclotron resonance plasma. The influences of pressure and nitrogen flow rate on physical and electrical properties were studied in order to minimize the hydrogen and oxygen content in the layers. The optimized layers were characterized by a refractive index of 1.98, a dielectric constant of 7.2, and Si/N ratio values of 0.78. The layers exhibited very good dielectric strength, which was confirmed by large breakdown fields of 12 MV/cm, very high resistivities of 1016 Omega cm, and maximum charges to breakdown values of 90 C/cm2. Increasing the deposition pressure and decreasing the N2 flow improved the SiN/Si interface, due to increased oxygen incorporation. The dominant conduction mechanism in the layers was the Poole-Frenkel effect. The critical field and the trap energy had similar dependencies on deposition pressure. Fowler-Nordheim tunneling occurred at high gate biases, for the layers deposited at the highest pressure of about 22 mTorr

Minority Carrier Tunneling and Stress-Induced Leakage Current for p+ gate MOS Capacitors with Poly-Si and PolySi0.7Ge0.3 Gate Material

In this paper the I-V conduction mechanism for gate injection (-V g), Stress-Induced Leakage Current (SILC) characteristics and time-to-breakdown (tbd) of PMOS capacitors with p+-poly-Si and poly-SiGe gate material on 5.6, 4.8 and 3.1 nm oxide thickness are studied. A model based on Minority Carrier Tunneling (MCT) from the gate is proposed for the I-V and SILC characteristics at -Vg of our devices. Time-to-breakdown data are presented and discusse

Optimization of nitridation conditions for high quality inter-polysilicon dielectric layers

Nitridation of deposited high temperature oxides (HTO) was studied to form high quality inter-polysilicon dielectric layers for embedded non volatile memories. Good quality dielectric layers were obtained earlier by using an optimized deposition of polysilicon and by performing a post-dielectric anneal in a rapid thermal processor. In the present paper the quality is further improved by means of optimization of the post-dielectric anneal. The influence of temperature, time and pressure during annealing on the electrical properties is investigated. Electrical characterization by means of charge-to-breakdown (Qbd) and I-V measurements on simple capacitor structures evaluates the electrical properties of the layers. It is shown that an (optimized) rapid thermal N2O anneal leads to a very high charge to breakdown (Qbd ¿ 25 C/cm2), low charge trapping and low leakage currents